Common components of a monolithic IC (integrated circuit) include interconnect structures such as metal line structures and via structures for electrically connecting integrated circuit devices formed on a semiconductor substrate, as known to one of ordinary skill in the art of integrated circuit fabrication. A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
However, copper cannot be easily patterned in a deposition and etch process, and thus, copper interconnect structures are typically formed by forming and filling openings with copper within dielectric material, as known to one of ordinary skill in the art of integrated circuit fabrication. FIG. 1 for example shows a dual damascene interconnect structure of the prior art including a via portion 102 and a line portion 104 formed on an underlying interconnect structure 106. The background of the invention and an embodiment of the present invention are described in reference to a dual damascene interconnect structure. However, the problems of the prior art and aspects of the present invention may be generalized to any type of interconnect structure such as a via structure or a metal line structure formed individually.
The underlying interconnect structure 106 is formed within an underlying dielectric material 108 that is formed on a semiconductor substrate 110. The via portion 102 and the line portion 104 of the dual damascene interconnect structure are formed within an upper layer of dielectric material 112 formed on the underlying dielectric material 108. The semiconductor substrate 110 is typically comprised of silicon, and the upper layer of dielectric material 112 and the underlying dielectric material 108 are typically comprised of silicon dioxide (SiO2) or a low-k dielectric material having a dielectric constant that is lower that the dielectric constant of silicon dioxide (SiO2).
The dual damascene interconnect structure is formed by filling a dual damascene opening having both a via opening for forming the via portion 102 and a trench line opening for forming the line portion 104 of the dual damascene interconnect structure, as known to one of ordinary skill in the art of integrated circuit fabrication. Such a dual damascene opening is filled with a conductive material to form the via portion 102 and the line portion 104 of the dual damascene interconnect structure, as known to one of ordinary skill in the art of integrated circuit fabrication. The via portion 102 electrically couples the underlying interconnect structure 106 to the line portion 104 of the dual damascene interconnect structure, as known to one of ordinary skill in the art of integrated circuit fabrication.
In the case such a conductive fill material is comprised of copper, a diffusion barrier material 114 is also typically formed to surround such copper fill material to prevent the diffusion of copper into the surrounding dielectric material 112. Copper is a mid-bandgap impurity in silicon, silicon dioxide, and other dielectric materials. Thus, copper may diffuse easily into these common integrated circuit materials to degrade the circuit performance of integrated circuits. To prevent such undesired diffusion of copper, the diffusion barrier material 114 is deposited to surround the copper interconnect at the interface between the copper interconnect and the surrounding material 112, as known to one of ordinary skill in the art of integrated circuit fabrication.
Further referring to FIG. 1, in the case that the underlying interconnect structure 106 is also comprised of copper, a diffusion barrier material 116 is formed to surround the underlying interconnect structure 106 from the underlying dielectric material 108. The diffusion barrier material 116 at the interface between the underlying interconnect structure 106 and the underlying dielectric material 108 prevents diffusion of copper from the underlying interconnect structure 106 into the underlying dielectric material 108.
Also referring to FIG. 1, a dielectric capping layer 118 is formed on the underlying interconnect structure 106 to further encapsulate the copper of the underlying interconnect structure 106. Similarly, a dielectric passivation layer 120 is formed on top of the line portion 104 of the dual damascene interconnect structure for further encapsulating the copper of the dual damascene interconnect structure. The dielectric capping layer 118 and the dielectric passivation layer 120 for example are comprised of silicon nitride (SiN), and copper does not diffuse as easily through such a material of the dielectric capping layer 118 and the dielectric passivation layer 120.
However, even though copper of the underlying interconnect structure 106 does not diffuse easily into the dielectric capping layer 118, copper atoms migrate along the interface 122 between the dielectric capping layer 118 and the copper line 106. Similarly, even though copper of the line portion 104 of the dual damascene interconnect structure does not diffuse easily into the dielectric passivation layer 120, copper atoms migrate along the interface 124 between the dielectric passivation layer 120 and the copper line 104. The copper atoms migrate along such interfaces 122 and 124 and may cause voiding in copper lines potentially creating an open circuit, especially when a void is formed beneath the via 102. Thus, such migration of copper along the interfaces 122 and 124 contributes to electromigration failure of the interconnect structures 102, 104, and 106.
Thus, a mechanism is desired for minimizing migration of atoms of the conductive material of an interconnect structure along the interface at the bottom of a dielectric capping layer or dielectric passivation layer formed on the interconnect structure.